1. Field of the Invention
The present invention relates to materials used in the manufacture of a semiconductor device which includes an array of transistors to achieve isolation between transistors. More particularly, the present invention relates to materials used in the manufacture of a semiconductor device containing a non-volatile memory array to achieve isolation between transistors.
2. Description of the Related Art
FIG. 1 shows a cross section of two NMOS transistors illustrating the typical configuration of materials used in the manufacture of a semiconductor device containing an array of transistors. The transistors are shown formed in a p-type silicon substrate 2. A first transistor 4 includes n-type source and drain implant regions 6 and 8 provided in the substrate 2. A polysilicon gate region 10 of the first transistor 4 is provided bridging the source 6 and drain 8 regions. The polysilicon gate region 10 is separated from the substrate 2 by a first inter-layer dielectric (ILD0) 22. A second transistor 14 includes n-type source and drain implant regions 16 and 18 provided in the substrate 2. A polysilicon gate region 20 of the second transistor 14 bridges the source and drain regions 16 and 18.
A field oxide region 24 is provided in the substrate 2 separating region 8 of the first transistor 4 and region 16 of the second transistor 14. A polysilicon layer 26 overlies the field oxide region 24 as well as a portion of the n-type regions 8 and 16. The polysilicon region 26 extends to serve as the gate region for other transistors (not shown) in the array, as do polysilicon regions 10 and 20.
The field oxide region 24 is provided to prevent field leakage between region 8 of the first transistor 4 and region 16 of the second transistor 14. A thickness "t" shown with field oxide layer 24 is set to control leakage current between transistors.
Thickness of the field oxide regions separating transistors typically dictates the distance separating each transistor. In explanation, as shown with respect to field oxide region 24, birds beak regions are formed during application of the field oxide regions. With greater thicknesses required for the field oxide regions to more limit field leakage, the birds beak regions extend further in a direction parallel to the surface of the substrate. With greater birds beak extensions, source and drain regions, such as regions 8 and 16 of adjacent transistors, must be separated by a greater distance. For greater device density, or more transistors provided per unit area of substrate, it is desirable to reduce the birds beak size.
Field leakage current can require the thickness of the field oxide to be significant in a large array of transistors. For memory cell transistors, voltage is typically pumped above a chip pin power supply voltage Vcc by charge pump circuitry on a chip. With significant current leakage, charge pump circuitry provided on the chip must be increased in size to supply necessary program voltages. Even with non-programmable transistors in a large array of transistors, significant additional current must be provided from a power supply, a condition which is undesirable.
With the field oxide layer thickness "t" controlled to set the degree of field leakage current, for a large array of transistors where it is typically desirable to increase array density, the thickness "t" of the field oxide layer may be undesirably large.
The ILD0 layer is typically composed of silicon dioxide, phosphorous silicate glass (PSG), tetraethyl orthosilicate (TEOS), borophosphorous tetraethyl orthosilicate (BPTEOS), or a combination of these materials. Although not shown, other layers of materials are applied above the ILD0 layer to fabricate an array of transistors. The ILD0 layer is provided between the substrate and a first metal layer. A subsequent dielectric layer ILD1 is provided between the first metal layer and a second metal layer, and a further dielectric layer ILD2 is provided between the second metal layer and a third metal layer.